Clocking scheme for reconfigurable wideband analog-to-digital converter

A clocking scheme for a reconfigurable wideband analog-to-digital converter (ADC) including a plurality of Delay Locked Loops (DLLs) arranged in parallel. Each DLL is responsive to an input clock signal and configured to selectively generate a plurality of output clock signals for controlling the op...

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Bibliographische Detailangaben
Hauptverfasser:	OMORI TOSHI, PEREIRA VICTORIA TABUENA, LINDER LLOYD FREDERICK, DAVIS BRANDON R, ROBL DOUGLAS A
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
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Beschreibung
Zusammenfassung:	A clocking scheme for a reconfigurable wideband analog-to-digital converter (ADC) including a plurality of Delay Locked Loops (DLLs) arranged in parallel. Each DLL is responsive to an input clock signal and configured to selectively generate a plurality of output clock signals for controlling the operation of the ADC.