Fabrication method for a chip package

Fabrication method for a chip package

An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodim...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: TSAI CHIA-LUN, CHENG CHIA-MING, YEOU LONG-SHENG
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MICROSTRUCTURAL TECHNOLOGY
PERFORMING OPERATIONS
PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
SEMICONDUCTOR DEVICES
TRANSPORTING
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Beschreibung
Zusammenfassung:An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.