Semiconductor device with reduced turn-on resistance and method of fabricating the same

A semiconductor device includes a gate pattern over source and drain regions. The gate pattern includes a first gate adjacent the source region and a second gate adjacent the drain region. A concentration of dopants in the first gate is higher than a concentration of dopants in the second gate. As a...

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Hauptverfasser: JANG JAE-JUNE, KIM HYUN-JU, PARK SEO-IN
Format: Patent
Sprache:eng
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Zusammenfassung:A semiconductor device includes a gate pattern over source and drain regions. The gate pattern includes a first gate adjacent the source region and a second gate adjacent the drain region. A concentration of dopants in the first gate is higher than a concentration of dopants in the second gate. As a result, channels are produced between the source and drain regions based on different threshold voltages.