Power architecture for low power modes in storage devices

A power control device comprising an always-on-domain (AOD) which includes control logic circuitry for controlling power from a power source, load switches, bias current generators. The power control device also includes, outside of the AOD, functional blocks. The control logic circuitry is configured to receive a signal to go into a lower power state, initiate a shut-down sequence of the load switches and the bias current generators of the AOD, to disable circuitry outside of the AOD, including the functional blocks of the power control device and loads controlled by the power control device, and operate in a low power state to detect a wake-up signal. The shut-down sequence may additionally include sequencing off voltage regulators outside of the AOD and a clock control inside the AOD.