Techniques for wafer-level processing of QFN packages

Techniques for wafer-level processing of QFN packages

Semiconductor package devices, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated...

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Bibliographische Detailangaben
Hauptverfasser: ZHOU TIAO, THAMBIDURAI KARTHIK, SERPIELLO JOSEPH W, XU YONG L, RAHIM MD. KAYSAR, KHANDEKAR VIREN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:Semiconductor package devices, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.