Smart discovery model in a serial attached small computer system topology
Methods, systems and processor-readable media are disclosed for implementing a "smart" discovery process in a data transfer regime having one or more expanders and one or more initiators. Data traffic associated with such a discovery process can be reduced and one or more of the initiators...
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| creator | CHANNAGIRI NAGENDRA RAGHAVENDRA DANAYAKANAKERI GIRIDHAR YENDIGIRI PRASHANT PRAKASH |
| description | Methods, systems and processor-readable media are disclosed for implementing a "smart" discovery process in a data transfer regime having one or more expanders and one or more initiators. Data traffic associated with such a discovery process can be reduced and one or more of the initiators can be prevented from blocking input/output to particular components in communication with the data transfer regime, thereby improving and completing the discovery process in an optimal time frame while enhancing the performance of the initiator(s). |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8990448B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8990448B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8990448B23</originalsourceid><addsrcrecordid>eNqNyjEOwjAMAMAsDAj4gz-AhKBDu1JRlbkwV1ZiIJJTR7FByu9ZeADTLbd21ylhMQhRvXyoVEgSiCEugKBUIjKgGfoXBdCEzOAl5bdRAa1qlMAkC8uzbt3qgay0-7lxMFxu_binLDNpRk8L2Xyf2q47NE17Pp7-KF-c6DTm</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Smart discovery model in a serial attached small computer system topology</title><source>esp@cenet</source><creator>CHANNAGIRI NAGENDRA RAGHAVENDRA ; DANAYAKANAKERI GIRIDHAR ; YENDIGIRI PRASHANT PRAKASH</creator><creatorcontrib>CHANNAGIRI NAGENDRA RAGHAVENDRA ; DANAYAKANAKERI GIRIDHAR ; YENDIGIRI PRASHANT PRAKASH</creatorcontrib><description>Methods, systems and processor-readable media are disclosed for implementing a "smart" discovery process in a data transfer regime having one or more expanders and one or more initiators. Data traffic associated with such a discovery process can be reduced and one or more of the initiators can be prevented from blocking input/output to particular components in communication with the data transfer regime, thereby improving and completing the discovery process in an optimal time frame while enhancing the performance of the initiator(s).</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150324&DB=EPODOC&CC=US&NR=8990448B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150324&DB=EPODOC&CC=US&NR=8990448B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHANNAGIRI NAGENDRA RAGHAVENDRA</creatorcontrib><creatorcontrib>DANAYAKANAKERI GIRIDHAR</creatorcontrib><creatorcontrib>YENDIGIRI PRASHANT PRAKASH</creatorcontrib><title>Smart discovery model in a serial attached small computer system topology</title><description>Methods, systems and processor-readable media are disclosed for implementing a "smart" discovery process in a data transfer regime having one or more expanders and one or more initiators. Data traffic associated with such a discovery process can be reduced and one or more of the initiators can be prevented from blocking input/output to particular components in communication with the data transfer regime, thereby improving and completing the discovery process in an optimal time frame while enhancing the performance of the initiator(s).</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEOwjAMAMAsDAj4gz-AhKBDu1JRlbkwV1ZiIJJTR7FByu9ZeADTLbd21ylhMQhRvXyoVEgSiCEugKBUIjKgGfoXBdCEzOAl5bdRAa1qlMAkC8uzbt3qgay0-7lxMFxu_binLDNpRk8L2Xyf2q47NE17Pp7-KF-c6DTm</recordid><startdate>20150324</startdate><enddate>20150324</enddate><creator>CHANNAGIRI NAGENDRA RAGHAVENDRA</creator><creator>DANAYAKANAKERI GIRIDHAR</creator><creator>YENDIGIRI PRASHANT PRAKASH</creator><scope>EVB</scope></search><sort><creationdate>20150324</creationdate><title>Smart discovery model in a serial attached small computer system topology</title><author>CHANNAGIRI NAGENDRA RAGHAVENDRA ; DANAYAKANAKERI GIRIDHAR ; YENDIGIRI PRASHANT PRAKASH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8990448B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>CHANNAGIRI NAGENDRA RAGHAVENDRA</creatorcontrib><creatorcontrib>DANAYAKANAKERI GIRIDHAR</creatorcontrib><creatorcontrib>YENDIGIRI PRASHANT PRAKASH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHANNAGIRI NAGENDRA RAGHAVENDRA</au><au>DANAYAKANAKERI GIRIDHAR</au><au>YENDIGIRI PRASHANT PRAKASH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Smart discovery model in a serial attached small computer system topology</title><date>2015-03-24</date><risdate>2015</risdate><abstract>Methods, systems and processor-readable media are disclosed for implementing a "smart" discovery process in a data transfer regime having one or more expanders and one or more initiators. Data traffic associated with such a discovery process can be reduced and one or more of the initiators can be prevented from blocking input/output to particular components in communication with the data transfer regime, thereby improving and completing the discovery process in an optimal time frame while enhancing the performance of the initiator(s).</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Smart discovery model in a serial attached small computer system topology |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T14%3A59%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHANNAGIRI%20NAGENDRA%20RAGHAVENDRA&rft.date=2015-03-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8990448B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |