Smart discovery model in a serial attached small computer system topology

Methods, systems and processor-readable media are disclosed for implementing a "smart" discovery process in a data transfer regime having one or more expanders and one or more initiators. Data traffic associated with such a discovery process can be reduced and one or more of the initiators can be prevented from blocking input/output to particular components in communication with the data transfer regime, thereby improving and completing the discovery process in an optimal time frame while enhancing the performance of the initiator(s).