Semiconductor timing improvement

Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip.