Reduced spacer thickness in semiconductor device fabrication

In aspects of the present disclosure, a reliable encapsulation of a gate dielectric is provided at very early stages during fabrication. In other aspects, a semiconductor device is provided wherein a reliable encapsulation of a gate dielectric material is maintained, the reliable encapsulation being present at early stages during fabrication. In embodiments, a semiconductor device having a plurality of gate structures is provided over a surface of a semiconductor substrate. Sidewall spacers are formed over the surface and adjacent to each of the plurality of gate structures, wherein the sidewall spacers cover sidewall surfaces of each of the plurality of gate structures. After performing an implantation sequence into the sidewall spacers using adjacent gate structures as implantations masks, shadowing lower portions of the sidewall spacers, an etching process is performed for removing implanted portions from the sidewall spacers, leaving lower shadowed portions of the sidewall spacer as shaped sidewall spacers.