Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit

A method for detecting rising and falling transitions of internal signals of an array or integrated circuit. An apparatus used in the method comprises a delay line with a plurality of first to Nth delay elements, latches, and first to Nth groups of logic gates. Each of the first to Nth groups of the logical gates includes an AND gate and a NOR gate. The method determines rising and falling signals based on output signals of the logic gates in the apparatus; in odd numbered groups of the logic gates, the AND gate detects the rising transition and the NOR gate detects the falling transition; in even numbered groups of the logic gates, the AND gate detects the falling transition and the NOR gate detects the rising transition.