Method, program, and apparatus for aiding wiring design

A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics. The computer further executes verifying, for...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: NISHIO YOSHITAKA, KONNO EIICHI, ORITA TAKAHIKO, SAKATA TOSHIYASU, OHTSUKA IKUO
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics. The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.