Bond pad configurations for controlling semiconductor chip package interactions

Bond pad configurations for controlling semiconductor chip package interactions

A semiconductor chip includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. The bond pad has an irregular configuration when viewed from above that corresponds to a first area portion that is defined by a first sub...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: RYAN VIVIAN W
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator RYAN VIVIAN W
description A semiconductor chip includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. The bond pad has an irregular configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. The second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and two sides of the first area portion are substantially aligned with and substantially flush with two respective sides of the second area portion.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8928146B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8928146B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8928146B23</originalsourceid><addsrcrecordid>eNrjZPB3ys9LUShITFFIzs9Ly0wvLUosyczPK1ZIyy8CCZUU5efkZOalKxSn5mYC-SmlySUgmYzMAqCu5OzE9FSFzLyS1KLEZLA-HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWgzUkpqXWhIfGmxhaWRhaGLmZGRMhBIAVh83qw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Bond pad configurations for controlling semiconductor chip package interactions</title><source>esp@cenet</source><creator>RYAN VIVIAN W</creator><creatorcontrib>RYAN VIVIAN W</creatorcontrib><description>A semiconductor chip includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. The bond pad has an irregular configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. The second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and two sides of the first area portion are substantially aligned with and substantially flush with two respective sides of the second area portion.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20150106&amp;DB=EPODOC&amp;CC=US&amp;NR=8928146B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20150106&amp;DB=EPODOC&amp;CC=US&amp;NR=8928146B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RYAN VIVIAN W</creatorcontrib><title>Bond pad configurations for controlling semiconductor chip package interactions</title><description>A semiconductor chip includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. The bond pad has an irregular configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. The second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and two sides of the first area portion are substantially aligned with and substantially flush with two respective sides of the second area portion.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPB3ys9LUShITFFIzs9Ly0wvLUosyczPK1ZIyy8CCZUU5efkZOalKxSn5mYC-SmlySUgmYzMAqCu5OzE9FSFzLyS1KLEZLA-HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWgzUkpqXWhIfGmxhaWRhaGLmZGRMhBIAVh83qw</recordid><startdate>20150106</startdate><enddate>20150106</enddate><creator>RYAN VIVIAN W</creator><scope>EVB</scope></search><sort><creationdate>20150106</creationdate><title>Bond pad configurations for controlling semiconductor chip package interactions</title><author>RYAN VIVIAN W</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8928146B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>RYAN VIVIAN W</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RYAN VIVIAN W</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Bond pad configurations for controlling semiconductor chip package interactions</title><date>2015-01-06</date><risdate>2015</risdate><abstract>A semiconductor chip includes at least one integrated circuit device and a bond pad that is electrically connected to the at least one integrated circuit device. The bond pad has an irregular configuration when viewed from above that corresponds to a first area portion that is defined by a first substantially regular geometric shape when viewed from above and a second area portion adjacent to the first area portion. The second area portion is located at a greater distance from a centerline of the semiconductor chip than any part of the first area portion when viewed from above, and two sides of the first area portion are substantially aligned with and substantially flush with two respective sides of the second area portion.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US8928146B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Bond pad configurations for controlling semiconductor chip package interactions
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T22%3A39%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RYAN%20VIVIAN%20W&rft.date=2015-01-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8928146B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true