Self-recovering bus signal detector

A detector circuit is disclosed that detects bus signal conditions. To detect a START condition, asynchronous sequential logic detects a first bus signal transition (e.g., from high to low) and a second bus signal (e.g., a high signal). The outputs of the asynchronous sequential logic are combined t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: FULLERTON IAN
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A detector circuit is disclosed that detects bus signal conditions. To detect a START condition, asynchronous sequential logic detects a first bus signal transition (e.g., from high to low) and a second bus signal (e.g., a high signal). The outputs of the asynchronous sequential logic are combined to produce a START signal that can be latched, so that the START signal can be used to wake up a system or for other purposes. To detect a STOP condition, asynchronous sequential logic is set by a transition (e.g., low to high) of the first bus signal and a second bus signal (e.g., a high signal), producing a STOP signal that can be used to reset the asynchronous sequential logic and the latch.