Innovative verification methodology for deeply embedded computational element

A circuit verification method for a logic circuit is presented. The method includes developing a first hardware description language (HDL) code representative of the logic circuit and, for an embedded portion of the logic circuit, developing a second HDL code representative of the embedded portion. The second HDL code includes a process of forcing inputs of the embedded portion to one or more known values. The method further includes operating a processing device in conjunction with the first and second HDL codes and verifying operation of the embedded portion in response to forcing the inputs to the logic circuit.