Semiconductor package having buried post in encapsulant and method of manufacturing the same

In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: JANG CHUL-YONG, KIM PYOUNG-WAN, LEE TEAK-HOON
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.