Differential serial interface for supporting a plurality of differential serial interface standards

An active capacitor multiplying circuit that in one embodiment comprises (i) a clock synthesis loop filter of at least second order comprising a series combination of a first resistor and a first capacitor, wherein the series combination is coupled between a first charge pump interface and ground, wherein the clock synthesis loop filter further comprises a second capacitor coupled between the first charge pump interface and the ground; (ii) a capacitor multiplying loop filter comprising a second capacitor coupled between a second charge pump interface and the ground, wherein the capacitor multiplying loop filter further comprises a second resistor coupled to the second charge pump interface and the second charge pump interface is coupled to the first charge pump interface; and (iii) an operational amplifier, driven by the first capacitor, for driving the second resistor, wherein a voltage presented at the first charge pump interface drives a voltage controlled oscillator.