Multi-dimension memory timing tuner

In embodiments of a multi-dimension memory timing tuner, a memory device controller that can be interfaced with one or more memory devices is coupled to a memory device for data communication with the memory device via a memory bus. Control registers maintain control register values that are adjustable to tune memory bus timing margins in multi-dimensions. The memory bus timing margins are tunable for implementation of a memory device controller with one or more of the memory devices. A memory timing tuner is implemented to adjust the control register values to tune the memory bus timing margins in the multi-dimensions.