Transparent processing core and L2 cache connection
Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed. |
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