Data processing apparatus and method for providing target address information for branch instructions

A data processing apparatus and method have a processor for executing instructions, and a prefetch unit for prefetching instructions from memory prior to sending those instructions to the processor for execution. A branch target cache structure has a plurality of entries, where the cache structure comprises an initial branch target cache having a first number of entries and a promoted entry branch target cache having a second number of entries. During lookup operation, both the initial entry branch target cache and the promoted entry branch target cache are accessed in parallel. For a branch instruction executed by the processor that does not currently have a corresponding entry in the branch target cache structure, allocation circuitry performs an initial allocation operation to allocate one of the entries in the initial entry branch target cache for storing the branch instruction information for that branch instruction.