Phase locked loop, CDR circuit, and receiving circuit

In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to perform phase comparison with a reference clock. Then, outputs of the first and second phase comparators are weighted by a result of the phase comparison of a receive signal and the feedback clock, and phase adjustment of the feedback clock is phase adjusted using the weighted outputs. Thereby, it is possible to lower a frequency of the reference clock and consequently to suppress power consumption.