Fine granularity power gating

An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.