Test structure for ILD void testing and contact resistance measurement in a semiconductor device

In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement inform...

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Hauptverfasser:	UTESS DIRK, CHUMAKOV DMYTRO
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING
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creator	UTESS DIRK CHUMAKOV DMYTRO
description	In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement information may be obtained on the basis of a reduced overall floor space of the test structure. In this manner, the complex manufacturing sequence for forming a contact level of a semiconductor device may be quantitatively estimated and monitored.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8598579B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8598579B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8598579B23</originalsourceid><addsrcrecordid>eNqNjDsOwjAQBdNQIOAOewEaUETS8hNIdIQ6rOyXyBJZR95Nzo8LDkD1ijczy-LdQI3U0uRsSqAuJro_zjTH4MnyF6QnFk8uirEzStCgxuJAA1izM0CMghCTYgiZ87mVMx5zcFgXi44_is1vVwVdL83ptsUYW-jIDgJrX8-qrKvyUB93-z-QL1Q8PV0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Test structure for ILD void testing and contact resistance measurement in a semiconductor device</title><source>esp@cenet</source><creator>UTESS DIRK ; CHUMAKOV DMYTRO</creator><creatorcontrib>UTESS DIRK ; CHUMAKOV DMYTRO</creatorcontrib><description>In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement information may be obtained on the basis of a reduced overall floor space of the test structure. In this manner, the complex manufacturing sequence for forming a contact level of a semiconductor device may be quantitatively estimated and monitored.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131203&DB=EPODOC&CC=US&NR=8598579B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131203&DB=EPODOC&CC=US&NR=8598579B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>UTESS DIRK</creatorcontrib><creatorcontrib>CHUMAKOV DMYTRO</creatorcontrib><title>Test structure for ILD void testing and contact resistance measurement in a semiconductor device</title><description>In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement information may be obtained on the basis of a reduced overall floor space of the test structure. In this manner, the complex manufacturing sequence for forming a contact level of a semiconductor device may be quantitatively estimated and monitored.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjDsOwjAQBdNQIOAOewEaUETS8hNIdIQ6rOyXyBJZR95Nzo8LDkD1ijczy-LdQI3U0uRsSqAuJro_zjTH4MnyF6QnFk8uirEzStCgxuJAA1izM0CMghCTYgiZ87mVMx5zcFgXi44_is1vVwVdL83ptsUYW-jIDgJrX8-qrKvyUB93-z-QL1Q8PV0</recordid><startdate>20131203</startdate><enddate>20131203</enddate><creator>UTESS DIRK</creator><creator>CHUMAKOV DMYTRO</creator><scope>EVB</scope></search><sort><creationdate>20131203</creationdate><title>Test structure for ILD void testing and contact resistance measurement in a semiconductor device</title><author>UTESS DIRK ; CHUMAKOV DMYTRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8598579B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>UTESS DIRK</creatorcontrib><creatorcontrib>CHUMAKOV DMYTRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>UTESS DIRK</au><au>CHUMAKOV DMYTRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Test structure for ILD void testing and contact resistance measurement in a semiconductor device</title><date>2013-12-03</date><risdate>2013</risdate><abstract>In complex semiconductor devices, the contact characteristics may be efficiently determined on the basis of a test structure which includes a combination of interconnect chain structures and a comb structure including gate electrode structures. Consequently, an increased amount of measurement information may be obtained on the basis of a reduced overall floor space of the test structure. In this manner, the complex manufacturing sequence for forming a contact level of a semiconductor device may be quantitatively estimated and monitored.</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING
title	Test structure for ILD void testing and contact resistance measurement in a semiconductor device
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T14%3A36%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=UTESS%20DIRK&rft.date=2013-12-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8598579B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true