Method of manufacturing vertical pin diodes

The invention concerns a method of manufacturing a vertical PIN diode comprising: providing an epitaxial wafer comprising a vertically stacked N-type layer, intrinsic layer and P-type layer; forming an anode contact of the vertical PIN diode by forming an anode metallization on a first portion of the P-type layer defining an anode region; forming an electrically insulating layer around the anode region such that a first portion of the intrinsic layer extends vertically between the N-type layer and the anode region and second portions of the intrinsic layer extend vertically between the N-type layer and the electrically insulating layer; forming a trench in the electrically insulating layer and in the second portions of the intrinsic layer so as to expose a portion of the N-type layer defining a cathode region and to define a sacrificial side-guard ring consisting of a portion of the electrically insulating layer that extends laterally between the trench and the anode region and laterally surrounds said anode region; and forming a cathode contact of the vertical PIN diode by forming a cathode metallization on the exposed portion of the N-type layer defining the cathode region.