Stacked semiconductor device and manufacturing method thereof

In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural...

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Bibliographische Detailangaben
Hauptverfasser: OMIZO SHOKO, IWAMI FUMIHIRO, YOSHIMURA ATSUSHI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.