Method and system for repartitioning a hierarchical circuit design

The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.