Dynamic phase alignment

A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of the clock signal. A further variation may limit the relative delay period to one-half clock cycle and...

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Bibliographische Detailangaben
Hauptverfasser: HOO YEONG SENG, KHOR CHOON KEAT, LIM SOON CHIEH
Format: Patent
Sprache:eng
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Zusammenfassung:A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of the clock signal. A further variation may limit the relative delay period to one-half clock cycle and may use a double inversion of the clock signal.