Integrated circuit arrangement for test inputs

Integrated circuit arrangement for test inputs

An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CURLEY LAWRENCE D, TONG CHING L, WEBEL TOBIAS, FRISHMUTH RONALD J, LUDEWIG RALF, BAUR ULRICH
Format: Patent
Sprache:eng
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.