Low voltage differential signal output stage

A low voltage differential signal (LVDS) output stage including a display signal digital circuit, a data parallel-to-serial (P2S) circuit and a transmitting circuit is provided. The display signal digital circuit generates a display signal and a display clock signal synchronous to each other according to a first frequency multiplication clock signal. The data P2S circuit samples the display signal according to a second frequency multiplication clock signal, so as to generate a serial data signal and a serial clock signal. The first frequency multiplication clock signal and the second frequency multiplication clock signal have a relationship of frequency multiplication. The data P2S circuit includes an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second frequency multiplication clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second frequency multiplication clock signal.