Page buffer circuit
A page buffer circuit includes: a main latch unit configured to have a main latch value which is dependent on a sub latch output signal, and output the main latch value to a first node; a sub latch unit configured to latch a voltage of a second node as a sub latch value in response to a storage enab...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A page buffer circuit includes: a main latch unit configured to have a main latch value which is dependent on a sub latch output signal, and output the main latch value to a first node; a sub latch unit configured to latch a voltage of a second node as a sub latch value in response to a storage enable signal, and generate the sub latch output signal according to the sub latch value when an output enable signal is activated; and a voltage determination unit connected between the first node and the second node, and configured to electrically connect or disconnect the first node to or from the second node in response to the storage enable signal, and determine a voltage level of the second node in response to the storage enable signal. |
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