Insulated gate semiconductor device with well region edge positioned within ring-shaped buffer trench

An insulated gate semiconductor device includes a semiconductor substrate, a drift layer on the substrate, a base layer on the drift layer, a ring-shaped gate trench dividing the base layer into a channel layer and a floating layer, an emitter region located in the channel layer to be in contact with a side surface of the gate trench, a well region located on the periphery of a cell area of the base layer and having a depth greater than a depth of the base layer, and a ring-shaped buffer trench located adjacent to and spaced from the gate trench in a length direction of the gate trench. An edge of the well region is located in an area enclosed by the buffer trench in the length direction of the gate trench.