Semiconductor memory device

In two inverters included in a latch in a memory cell, the source or drain of a PMOS load transistor connected to a memory node is cut off, and the source or drain of an NMOS drive transistor connected to another memory node is cut off, whereby internal data is fixed or permanently stored in the memory cell while ensuring a resistance to damage to the gate of the transistor and without impairing the regularity of the layout.