Stackable multi-chip package system

Stackable multi-chip package system

A stackable multi-chip package system is provided including forming a first external interconnect having a first through hole and a second external interconnect having a second through hole, forming a first package subassembly having the first external interconnect and a first integrated circuit die...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: YEE JAE HAK, LEE KOO HONG
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A stackable multi-chip package system is provided including forming a first external interconnect having a first through hole and a second external interconnect having a second through hole, forming a first package subassembly having the first external interconnect and a first integrated circuit die, forming a second package subassembly having the second external interconnect and a second integrated circuit die, mounting the second package subassembly over the first package subassembly, and molding the first package subassembly and the second package subassembly.