Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set

Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals;...

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Bibliographische Detailangaben
Hauptverfasser: GOODHUE GREGORY, SHRIVASTAVA PANKAJ, KHAN ATA, DING ZHIMIN, MACKENNA CRAIG
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.