Data input/output circuit and method of semiconductor memory apparatus

A first timing control unit controls an active timing of a first control signal to output a first driving control signal. A first data input/output unit transmits write data from a data input/output buffer to a global input/output line or transmits read data from the global input/output line to the data input/output buffer, in response to the first driving control signal. A second timing control unit controls an active timing of a second control signal to output a second driving control signal. A second data input/output unit transmits the write data from the global input/output line to a local input/output line or transmits the read data from the local input/output line to the global input/output line, in response to the second driving control signal.