Digital CMOS circuit with noise cancellation

A system is provided with a digital complementary-metal-oxide-semiconductor (CMOS) device and a noise cancellation circuit. The CMOS device has a first interface to accept a binary logic input signal, a second interface to accept a source current, a third interface to supply a binary logic output signal, and a fourth interface connected to a first dc voltage (e.g., ground) to sink current. A first resistor is interposed between a second dc voltage (e.g., Vdd), with a potential higher than the first dc voltage, and the second interface of the CMOS device. The noise cancellation circuit has a first interface connected to the second dc voltage. The noise cancellation circuit high pass filters ac noise on the second dc voltage, amplifies the filtered noise, and supplies the amplified noise at a second interface connected to the second interface of the CMOS device.