Circuit and method for efficient memory repair
A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes n number of groups o...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes n number of groups of the failing memory output data during n cycles using analysis logic and calculating a repair solution. Normal operations can be resumed. |
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