Semiconductor device including arrangement to control connection height and alignment between a plurity of stacked semiconductor chips

A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a...

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Bibliographische Detailangaben
Hauptverfasser: TANIE HISASHI, CHIWATA NOBUHIKO, WAKANO MOTOKI, ITABASHI TAKEYUKI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection.