Wafer level surface passivation of stackable integrated circuit chips

Wafer level surface passivation of stackable integrated circuit chips

An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a...

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Bibliographische Detailangaben
Hauptverfasser: MCELREA SIMON J. S, DU YONG, CASKEY TERRENCE, PAN WEIPING, VILLAVICENCIO GRANT, MELCHER DEANN EILEEN, CO REYNALDO, ANDREWS, JR. LAWRENCE DOUGLAS, CRANE SCOTT JAY, LIU ZONGRONG, MCGRATH SCOTT
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).