Optimized selection of memory chips in multi-chips memory devices

A method includes accepting a definition of a type of multi-unit memory device (28) including a set of memory units (24), each having a respective nominal storage capacity, the definition specifying a target memory size of the memory device such that a sum of nominal storage capacities of the memory...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: SHALVI OFIR
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A method includes accepting a definition of a type of multi-unit memory device (28) including a set of memory units (24), each having a respective nominal storage capacity, the definition specifying a target memory size of the memory device such that a sum of nominal storage capacities of the memory units in the set is equal to the target memory size. A plurality of the memory units is accepted. The memory units have respective actual storage capacities, at least some of which differ from the respective nominal storage capacity. Multi-unit memory devices including respective sets of the memory units are assembled, such that at least one of the sets includes at least a first memory unit having a first actual capacity that is less than the respective nominal capacity and at least a second memory unit having a second actual capacity that is greater than the nominal capacity.