Method for fabricating a transistor including a polysilicon layer formed using two annealing processes

Method for fabricating a transistor including a polysilicon layer formed using two annealing processes

A transistor includes a substrate, an active region including a source region, a channel region, and a drain region which are crystallized using an SGS crystallization method and are formed on the substrate so that a grain size of a first annealed portion and a second annealed portion are different...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: YANG TAEHOON, JUNG SEIHWAN, LISACHENKO MAXIM, LEE KIYONG, PARK BYOUNGKEON, SEO JINWOOK
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A transistor includes a substrate, an active region including a source region, a channel region, and a drain region which are crystallized using an SGS crystallization method and are formed on the substrate so that a grain size of a first annealed portion and a second annealed portion are different from each other, a gate insulating layer formed on the active region, and a gate electrode formed on the gate insulating layer.