Analog-to-digital converter timing circuits

An analog-to-digital converter timing circuit disclosed herein uses a clock generation circuit that makes the analog-to-digital converter insensitive to input clock duty cycle. Minimum clock jitter is added to the clock signal while propagating through the disclosed circuit. A method and system are...

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Bibliographische Detailangaben
Hauptverfasser:	HERNES BJORNAR, ANDERSEN TERJE NORTVEDT, TELSTO FRODE
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTING COUNTING DECODING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:	An analog-to-digital converter timing circuit disclosed herein uses a clock generation circuit that makes the analog-to-digital converter insensitive to input clock duty cycle. Minimum clock jitter is added to the clock signal while propagating through the disclosed circuit. A method and system are also disclosed to clock an interleaved pipelined ADC such that the operation is insensitive to input clock duty cycle and such that the clock jitter on the sampling clock edges is minimized.