Sequential element low power scan implementation

Sequential element low power scan implementation

A sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: BROWN JEFF S, BYRN JONATHAN, TURNER MARK F
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
PULSE TECHNIQUE
TESTING
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.