Method for auto-correction of errors in a solid-state memory system

A method for auto-correction of errors in an array of solid-state storage devices having a plurality of storage channels dedicated to storing parity data to provide fault tolerance for a loss of at least two of the plurality of storage channels. A read operation from the storage channels transfers d...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MANNING JOHN GORDON, MCBRYDE LEE DOUGLAS, PISZCZEK MICHAEL J, FERNANDES CEDRIC T, HARKER WILLIAM JOSEPH
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A method for auto-correction of errors in an array of solid-state storage devices having a plurality of storage channels dedicated to storing parity data to provide fault tolerance for a loss of at least two of the plurality of storage channels. A read operation from the storage channels transfers data to a plurality of channel memories. The data in the channel memories is checked to confirm the data is valid. Responsive to detection of invalid data, the data may be tested to identify the storage channel in error, including sequentially excluding data read form a different one of the plurality of channel memories from a parity check and determining the validity of data from remaining channel memories. If valid data is obtained, the storage channel from which the data was excluded is identified as the storage channel in error.