Power integrated circuit with high insensitivity to parasitic inductances of wires for connection to a package and package for said integrated circuit
The present disclosure relates to an integrated circuit and a package on which such integrated circuit is placed, the latter having a power output stage, at least one first pad, one second pad and one drive circuit for driving said power output stage, wherein the integrated circuit is characterized...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | The present disclosure relates to an integrated circuit and a package on which such integrated circuit is placed, the latter having a power output stage, at least one first pad, one second pad and one drive circuit for driving said power output stage, wherein the integrated circuit is characterized in that it has at least one additional third pad, other than said at least one first and said at least one second pads, said drive circuit being electrically coupled between said at least one third pad and said power output stage. |
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