Methodologies and tool set for IDDQ verification, debugging and failure diagnosis

Quiescent supply current (IDDQ) verification, prediction, and debugging of low power semiconductor devices are enhanced by IDDQ defect diagnosis. If all IDDQ patterns fail verification, per module analysis is performed to sort out potential module design issues or cell constraint issues. For issues of missing constraints, and cell design or implementation issues leading to extra leakage that could be avoided by adding constraints, there are usually IDDQ patterns that correlate with expectations, and patterns that do not, due to the random nature of unconstrained scan cell values as determined by the pattern generation tool. Differentiating good and bad IDDQ patterns can identify root causes of IDDQ issues and additional constraints to fix the bad IDDQ vectors. These verification procedures are achieving IDDQ test success and short time to market, as well as significantly faster time to volume and improved yields because of having a higher quality and better-controlled IDDQ test.