Timing-optimal placement, pin assignment, and routing for integrated circuits

Techniques for timing-optimal placement, pin assignment, and routing for integrated circuits are described herein. According to one embodiment, a list of paths providing implementation possibilities is constructed. A means is provided for removing paths from the list as well as a means for committing paths to the implementation if such paths are required for making the circuit implementation valid. Paths with worst case attributes are iteratively removed from the list until all paths in the list are committed to the implementation. Other methods and apparatuses are also described.