Symbol timing recovery circuit

An analog-to-digital (A/D) converter samples an input signal with a first clock. An finite impulse response (FIR) filter generates data at a zero-crossing point/data decision point from the sampled data. A decimation circuit decimates an output of the FIR filter 2 with a second clock. A phase comparator detects a phase error of the output signal of the decimation circuit. An Numerically Controlled Oscillator (NCO) (A/D) generates a phase signal by integrating the phase error. A tap coefficient computing unit generates tap coefficients of the FIR filter in accordance with the phase signal. In the NCO, if the phase signal exceeds " ", "2 +the phase error" is subtracted from the phase signal.