Failure analysis based on time-varying failure rates

Failure analysis method and apparatus using failure rate data in coordination with the power on hours to more efficiently resolve computer system failures without occupying system memory or processor bandwidth. In response to a system failure, a baseboard management controller (BMC) notes the time o...

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1. Verfasser: SUFFERN EDWARD S
Format: Patent
Sprache:eng
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Zusammenfassung:Failure analysis method and apparatus using failure rate data in coordination with the power on hours to more efficiently resolve computer system failures without occupying system memory or processor bandwidth. In response to a system failure, a baseboard management controller (BMC) notes the time of failure and the elapsed operating time of system components. In response to a failure of the computer system, the BMC accesses industry standard failure rate data correlating the elapsed operating time with the probability of failure for each component. By cross-referencing the time of failure with the failure rate data, the BMC automatically determines the probability of failure of each component at the time of failure of the computer system. The BMC generates a component replacement list identifying the component that currently has the highest probability of failure.