On-die anti-resonance structure for integrated circuit

A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.

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1. Verfasser: CHEN HOUFEI
Format: Patent
Sprache:eng
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Zusammenfassung:A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.