Implementing vertical airgap structures between chip metal layers

A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first layer of silicon dioxide dielectr...

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Bibliographische Detailangaben
Hauptverfasser:	GIBBS NATHANIEL JAMES, FOX BENJAMIN AARON, MAKI ANDREW BENSON, AGUADO GRANADOS AXEL, TIMPANE TREVOR JOSEPH
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first layer of silicon dioxide dielectric above the first metal layer. A second layer of silicon dioxide dielectric is deposited and the vertical air gap is sealed. A next trace layer is etched from the second layer of silicon dioxide dielectric and a via opening is etched from the second and first layers of silicon dioxide dielectric. Then metal is deposited into the next trace layer and metal is deposited into the via opening.